application note AN29 AN29-1 interfacing the x24c44/45 novrams to the motorola 6805 microcontroller by applications staff, july 1992 the following code demonstrates how the xicor x24c44/45 serial novrams could be interfaced to the 6805 microcontroller family when connected as shown in figure 1. the interface uses port a, with the pa3 pin connected to the serial clock (sk), pa2 connected to chip enable (ce), and pa4 connected to both serial data input (si) and serial data output (so) of the novram. additional code can be found on the xicor web site at http://www.xicor.com that will implement interfaces between motorola microcontrollers and other xicor serial devices. vcc u2 6805 vpp 8 vstby 7 ex 6 xt 5 reset 2 int1 3 pa0 33 pa1 34 pa2 35 pa3 36 pa4 37 pa5 38 pa6 39 pa7 40 pb0 25 pb1 26 pb2 27 pb3 28 pb4 29 pb5 30 pb6 31 pb7 32 pc0 9 pc1 10 pc2 11 pc3 12 pc4 13 pc5 14 pc6 15 pc7 16 pd0 24 pd1 23 pd2 22 pd3 21 pd4 20 pd5 19 pd6 18 pd7 17 u1 x24c44 di 3 ce 1 sk 2 recall 6 store 7 do 4 fi g ure 1. t y pical hardware connection for interfacin g an x24c44 to a 6805 microcontroller
xicor application note AN29-2 AN29 ******************************************************************************* * this code was designed to demonstrate how the x24c44 could be interfaced to * * the 68hc05 microcontroller. the interface uses 3 lines from port a (pa2, * * pa3, and pa4) to communicate. the di and do pins on the x24c44 are tied * * together which allows 1 less port line to be used. * * * * the code shown demonstrates rcl, wren, read, write, and store * * instructions. the remaining instructions (wrds and enas) can be issued * * using the same routine as other non-data instructions. * * * * the program issues a sequence of instructions to read the contents of * * address 5 and stores the same value in address 9. the sequence of * * instructions is as follows : * * * * 1. rcl sets the previous recall latch * * 2. wren sets the write enable latch * * 3. read data from address 5 is read * * 4. write the data read during step 3 is written to address 9 * * 5. sto the ram's contents is transfered to the eeprom * * * * data transfer is performed with the most significant bit first. * ******************************************************************************* skbit equ 3 mask indicating portd sk position cebit equ 2 mask indicating portd ce position diobit equ 4 mask indicating portd data position dout equ $1c mask to make di/o an output din equ $0c mask to make di/o an input dmask equ $10 mask to look for data from x24c44 wrds equ $80 reset write enable latch sto equ $81 transfers from ram to eeprom sleep equ $82 places part into power down mode write equ $83 ram write wren equ $84 set write enable latch rcl equ $85 transfers from eeprom to ram, resets * write enable latch read equ $86 ram read ddra equ $04 data direction register for port a porta equ $00 address for port a addr equ $80 location for x24c44 address to access inst equ $81 instruction for part rwdat equ $82 location for x24c44 data transfered count equ $84 counter variable temp1 equ $85 ********************************************* * reset vector to beginning of program code * ********************************************* org $1ffe reset vector to program entry point fdb $0100 ****************************** * start of program execution * ****************************** org $0100 beginning of executable code
AN29-3 xicor application note AN29 begin: lda #dout sta ddra make ce, sk, di/o outputs lda #$00 sta porta initialize ce, sk, di/o to zeros lda #rcl perform a recall to set sta inst the recall latch jsr cehigh jsr outbyt jsr celow lda #wren perform a write enable to set sta inst the write enable latch jsr cehigh jsr outbyt jsr celow lda #$05 read the contents of address 5 sta addr the value read will be in stored jsr rdwrd in rwdata lda #$09 write the data just read into sta addr address 9 jsr wrwrd lda #sto perform a store operation sta inst jsr cehigh jsr outbyt jsr celow bra * loop until reset ****************************************************** * write the word specified in rwdat. the address to * * be written is specified in addr. * ****************************************************** wrwrd: jsr cehigh write value in rwdata into location lda addr specified in addr lsla justify address in instruction lsla lsla ora #write mask in write instruction sta inst jsr outbyt send write instruction to dut lda rwdat sta inst jsr outbyt send in upper byte of data lda rwdat+1 sta inst jsr outbyt send in lower byte of data jsr celow rts ********************************************************* * read the word at the location specified in addr. the * * data read will be placed in rwdat. * ********************************************************* rdwrd: jsr cehigh read the address specified in addr lda addr lsla justify address to read lsla lsla
xicor application note AN29-4 AN29 ora #read mask in read instruction sta inst jsr send7 send in 7 bits of read instruction lda #din make data line an input sta ddra jsr clock send eighth clock pulse for read instruction lda #$10 prepare to shift in 16 bits sta count bitx: clc assume bit is going to be a zero (clear carry) lda porta read bit value and #dmask mask bit out of byte read beq no1 leave carry flag alone if bit is a 0 sec set carry if bit is a 1 no1: rol rwdat+1 roll carry flag into data word rol rwdat jsr clock send a clock pulse dec count loop until 16 bits are read bne bitx lda #dout make data line an output sta ddra jsr celow bring ce low rts ****************************************************** * send data out to the part. the data to be sent is * * located in inst. * ****************************************************** send7: lda #$07 shift out 7 bits for read instruction sta count bra loopo outbyt: lda #$08 prepare to shift out 8 bits sta count loopo: rol inst bcc is0 jump if data should be 0 bset #diobit,porta send 1 to di/o bra is1 is0: bclr #diobit,porta send 0 to di/o is1: jsr clock send clock signal dec count bne loopo loop until all 8 bits have been sent rts ***************** * bring ce high * ***************** cehigh: bset #cebit,porta bring ce high rts **************** * bring ce low * **************** celow: bclr #diobit,porta bring data line low bclr #cebit,porta bring ce low rts
AN29-5 xicor application note AN29 ************************ * issue a clock pulse. * ************************ clock: bset #skbit,porta bring sk high bclr #skbit,porta bring sk low rts
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